CL RC632 Reset

[Vuha]

Hi OpenPCD Folks,

I am a RFID development engineer. At moment, I am working with CL RC632 too. My fimrware is based on originate NXP source. Our company profile is access control systems. THe RFID reader should be operated non-stop, without error. For this purpose, I have created warm reset in RFID reader (it is only microcontroller restart via watchdog) to emulate malfunction from different situations.

After tests, I run into a problem. Sometimes (1-2% of all action), PcdReset() is frozen at "wait until reset command recognized". Beside this, sometimes I can read byte of 0x00 after SleepUs(100); (at first SPI transaction).

Because, NXP has not defined exactly, what is happend, when there is a SPI transaction under Hard Power Down Phase (tPD). As I know, tPD takes different times design-by-design. This behaviour depend on the used crystal. End of Hard Power Down has depend on when the oscillator is running stable. In my board, it takes 436us (from fallling edge of RSTPD to 90% of voltage of OSCOUT). Also there is a few SPI reading process under it.

Have you ever seen problems with CL RC632 startup sequence with your algorithm?

The originate NXP BasicFunctionalLibrary uses different algorithm to reset chip against you:

///////////////////////////////////////////////////////////////////////
//      M I F A R E   M O D U L E   R E S E T 
///////////////////////////////////////////////////////////////////////
char PcdReset(void)
{
   char status = MI_OK;

   SleepMs(500);        // wait after POR    
   READER_RESET;        // reset reader IC
   SleepMs(100);        // wait
   READER_CLEAR_RESET; // clear reset pin
   SleepUs(100);

   // wait until reset command recognized
   while (((ReadRawRC(RegCommand) & 0x3F) != 0x3F));

   // while reset sequence in progress
   while ((ReadRawRC(RegCommand) & 0x3F));

   WriteRawRC(RegPage,0x00); // Dummy access in order to determine the bus 
                             // configuration
   // necessary read access 
   // after first write access, the returned value
   // should be zero ==> interface recognized
   if (ReadRawRC(RegCommand) != 0x00)
   {                           
       status = MI_INTERFACEERR;
   }

   return status;
}


Your solution is

void rc632_reset(void)
{
 volatile int i;

 rc632_power(0);
 for (i = 0; i < 0xffff; i++)
  {}
 rc632_power(1);

 /* wait for startup phase to finish */
 while (1) {
  u_int8_t val;
  opcd_rc632_reg_read(NULL, RC632_REG_COMMAND, &val);
  if (val == 0x00)
   break;
 }

 /* turn off register paging */
 opcd_rc632_reg_write(NULL, RC632_REG_PAGE0, 0x00);
}
 

As I see your source, you wait until byte of 0x00 from chip.

Unfortunately, your algorithm has not resolved my problem. Because, I sometimes can read byte of 0x00 from chip under tPD. The firmware believes that 632 is ready and runs initialization before chip is not ready.

The NXP offer, that it should be wait for 0x3F before, and after this wait for 0x00 (ready state). However, it runs speed of SPI problem. Speed should be at least 3 times faster, because of 512+128 CLK = 47.2us (3 pcs SPI transaction under this time for proper detect). Of course, in this situation, ITs should be disabled.

Unfortunately, documents of NXP don't talk about this.

What is your opinion about this reset problem?
What is your experiments?
Could you tell me, what is the CLRC632 answare under Hard Power Down state after falling endge of RSTPD and before Reset Phase?

Thanks in advance

--------------------------------------------------------------------------------

Attila Varhelyi 
Development Engineer
SEAWING CONTROLS LTD.
H-8000, Szekesfehervar, Budai u 139.
Hungary
Tel: +36 22-510-170
Fax: +36 22-510-171
Email: varhelyi at seawing.hu
Web: www.seawing.hu
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