Clock generation for SSC

[hubert-b at gmx.de]

It seems that OpenPICC generates the clock for the Synchronous Serial Controller (SSC) using the Timer Counter (TC). Whats very confusing is that 2 TC-Channels are used for clock generation because generating a clock of about 423 kHz is also possible using only one TC-Channel. Furthermore, the SSC can generate a clock itself in dependence of the Master Clock (MCK)

Ok let me sum up my above words: Generating a SSC-Clock of 423 kHz is possible using

1) The SSC itself with a Master Clock Divider of 32 (if MCK = 13.56 MHz)
2) Using the Timer Counter (TC) with only one channel
3) Using the Timer Counter (TC) with two channels (this is the way its done right now)

The question now is: Why did you use the third way? What disadvantages do the other possibilities have? Or what is the advantage of the third way?

Best Regards
HubertB
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