Clock generation for SSC

[hubert-b at gmx.de]

On Tue, 2008-10-07 at 11:55 +0200, hubert-b at gmx.de wrote:
> It seems that OpenPICC generates the clock for the Synchronous Serial Controller (SSC) using the Timer Counter (TC).
> Whats very confusing is that 2 TC-Channels are used for clock generation because generating a clock of about 423 kHz
> is also possible using only one TC-Channel. Furthermore, the SSC can generate a clock itself in dependence of the 
> Master Clock (MCK)
> 
> Ok let me sum up my above words: Generating a SSC-Clock of 423 kHz is possible using
> 
> 1) The SSC itself with a Master Clock Divider of 32 (if MCK = 13.56 MHz)
> 

Ok meanwhile I discovered that MCK is something about 48 MHz.

> 2) Using the Timer Counter (TC) with only one channel
> 3) Using the Timer Counter (TC) with two channels (this is the way its done right now)
> 

The question why the clock is generated using the 3rd way still exists. Anybody out there? Who can help?

> The question now is: Why did you use the third way? What disadvantages do the other possibilities have? Or what is the
> advantage of the third way?
> 
> Best Regards
> HubertB
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