Clock generation for SSC

[Milosch Meriac]

Dear Hubert,

hubert-b at gmx.de wrote:
>> 1) The SSC itself with a Master Clock Divider of 32 (if MCK = 13.56 MHz)

This isn't an option because we want to sample synchronously to the carrier.

> Ok meanwhile I discovered that MCK is something about 48 MHz.

Yes - this is the only clock option when USB support is needed like in
our case.

>> 2) Using the Timer Counter (TC) with only one channel

The 13.56MHz reader carrier clock is fed into PA28 (TCLK1) to allow
carrier synchronous sampling of MFOUT data and generation of MFIN data.
The input of timer1 runs therefore with 13.56MHz clock and its output is
fed into RK (Receice Clock) of the SSC and can be also used as transmit
clock.

As the FIQ is also on the same pin as the RK of the SSC this allows nice
high speed and real time interrupt routines for custom reader protocols.

>> 3) Using the Timer Counter (TC) with two channels (this is the way its done right now)
> 
> The question why the clock is generated using the 3rd way still exists. Anybody out there? Who can help?

The idea behind having two cascaded timers for the 13.56MHz carrier
clock was AFAIR to be able to switch between MFIN generation (847.5kHz
subcarrier based or higher) and MFOUT sampling (105.9kHz etc.) without
the need of reconfiguring the timer.

Warmest regards,
--
Milosch